Method for fabricating an array of ultra-small pores for chalcogenide memory cells

ABSTRACT

A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared. The pores thus defined are further equally spaced from adjacent pores by a spacing ranging from approximately 0.25 to 0.5 microns. The pores thus defined may then be used to fabricate an array of chalcogenide memory cells.

This application is a Continuation of application Ser. No. 09/309,622,filed May 11, 1999, now U.S. Pat. No. 6,300,684 which is a Continuationof application Ser. No. 08/846,728, filed Apr. 30, 1997, which issued asU.S. Pat. No. 6,002,140 on Dec. 14, 1999, which is a Divisional ofapplication Ser. No. 08/473,077, filed Jun. 7, 1995, which issued asU.S. Pat. No. 5,879,955 on Mar. 9, 1999.

BACKGROUND OF THE INVENTION

The present invention relates generally to semiconductor fabricationtechniques and, more particularly, to a method for fabricatingultra-small pores for use in phase or state changeable memory devicessuch as, for example, chalcogenide memory cells.

The use of electrically writable and erasable phase change materials(i.e., materials which can be electrically switched between generallyamorphous and generally crystalline states or between differentresistive states while in crystalline form) for electronic memoryapplications is known in the art and is disclosed, for example, in U.S.Pat. No. 5,296,716 to Ovshinsky et al., the disclosure of which isincorporated herein by reference. U.S. Pat. No. 5,296,716 is believed togenerally indicate the state of the art, and to contain a discussion ofthe current theory of operation of chalcogenide materials.

Generally, as disclosed in the aforementioned Ovshinsky patent, suchphase change materials can be electrically switched between a firststructural state where the material is generally amorphous and a secondstructural state where the material has a generally crystalline localorder. The material may also be electrically switched between differentdetectable states of local order across the entire spectrum between thecompletely amorphous and the completely crystalline states. That is, theswitching of such materials is not required to take place betweencompletely amorphous and completely crystalline states but rather thematerial can be switched in incremental steps reflecting changes oflocal order to provide a “gray scale” represented by a multiplicity ofconditions of local order spanning the spectrum from the completelyamorphous state to the completely crystalline state.

The material exhibits different electrical characteristics dependingupon its state. For instance, in its amorphous state the materialexhibits a lower electrical conductivity than it does in its crystallinestate.

These memory cells are monolithic, homogeneous, and formed ofchalcogenide material selected from the group of Te, Se, Sb, Ni, and Ge.Such chalcogenide materials can be switched between numerouselectrically detectable conditions of varying resistivity in nanosecondtime periods with the input of picojoules of energy. The resultingmemory material is truly non-volatile and will maintain the integrity ofthe information stored by the memory cell without the need for periodicrefresh signals. Furthermore the data integrity of the informationstored by these memory cells is not lost when power is removed from thedevice. The subject memory material is directly overwritable so that thememory cells need not be erased (set to a specified starting point) inorder to change information stored within the memory cells. Finally, thelarge dynamic range offered by the memory material provides for the grayscale storage of multiple bits of binary information in a single cell bymimicking the binary encoded information in analog form and therebystoring multiple bits of binary encoded information as a singleresistance value in a single cell.

The operation of chalcogenide memory cells requires that a region of thechalcogenide memory material, called the chalcogenide active region, besubjected to a current pulse typically with a current density betweenabout 10⁵ and 10⁷ amperes/cm², to change the crystalline state of thechalcogenide material within the active region contained within a smallpore. This current density may be accomplished by first creating a smallopening 1 in a dielectric material 2 which is itself deposited onto alower electrode material 3 as illustrated in FIG. 1. A second dielectriclayer 4, typically of silicon nitride, is then deposited onto thedielectric layer 2 and into the opening 1. The second dielectric layer 4is typically on the order of 40 Angstroms thick. The chalcogenidematerial 5 is then deposited over the second dielectric material 4 andinto the opening 1. An upper electrode material 6 is then deposited overthe chalcogenide material 5. Carbon is a commonly used electrodematerial although other materials have also been used, for example,molybdenum and titanium nitride. A conductive path is then provided fromthe chalcogenide material 5 to the lower electrode material 3 by forminga pore 7 in the second dielectric layer 4 by the well known process ofpopping. Popping involves passing an initial high current pulse throughthe structure which passes through the chalcogenide material 5 and thenprovides dielectric breakdown of the second dielectric layer 4 therebyproviding a conductive path via the pore 7 through the memory cell.

Electrically popping the thin silicon nitride layer 4 is not desirablefor a high density memory product due to the high current required andthe large amount of testing time that is required for the popping.

The active regions of the chalcogenide memory cells within the pores arebelieved to change crystalline structure in response to applied voltagepulses of a wide range of magnitudes and pulse durations. These changesin crystalline structure alter the bulk resistance of the chalcogenideactive region. The wide dynamic range of these devices, the linearity oftheir response, and lack of hysteresis provide these memory cellswith-multiple bit storage capabilities.

Factors such as pore dimensions (diameter, thickness, and volume),chalcogenide composition, signal pulse duration and signal pulsewaveform shape have an effect on the magnitude of the dynamic range ofresistances, the absolute endpoint resistances of the dynamic range, andthe voltages required to set the memory cells at these resistances. Forexample, relatively thick chalcogenide films (e.g., about 4000Angstroms) will result in higher programming voltage requirements (e.g.,about 15-25 volts), while relatively thin chalcogenide layers (e.g.,about 500 Angstroms) will result in lower programming voltagerequirements (e.g., about 1-7 volts). The most important factor inreducing the required programming voltage is the pore cross sectionalarea.

The energy input required to adjust the crystalline state of thechalcogenide active region of the memory cell is directly proportionalto the dimensions of the minimum lateral dimension of the pore (e.g.,smaller pore sizes result in smaller energy input requirement).Conventional chalcogenide memory cell fabrication techniques provide aminimum lateral pore dimension, diameter or width of the pore, that islimited by the photolithographic size limit. This results in pore sizeshaving minimum lateral dimensions down to approximately 1 micron.

The present invention is directed to overcoming, or at least reducingthe affects of, one or more of the problems set forth above. Inparticular, the present invention provides a method for fabricatingultra-small pores for chalcogenide memory cells with minimum lateraldimensions below the photolithographic limit thereby reducing therequired energy input to the chalcogenide active region in operation.The present invention further eliminates the unpredictable prior artmethod of pore formation by electrical breakdown of a thin siliconnitride layer to form a small pore. As a result, the memory cells may bemade smaller to provide denser memory arrays, and the overall powerrequirements for the memory cell are minimized.

SUMMARY OF THE INVENTION

The present invention provides a new method for fabricating an array ofultra-small pores for use in chalcogenide memory cells. A layer of afirst material is applied onto a substrate. A portion of the layer ofthe first material is then removed to define an upper surface withvertical surfaces extending therefrom to a lower surface in the firstlayer of the first material. A fixed layer of a second material is thenapplied onto the vertical surfaces of the first layer of the firstmaterial. The fixed layer of the second material has a first thickness.A second layer of the first material is then applied onto the fixedlayer of the second material. The fixed layer of the second material isthen removed to define an array of pores in the first material layers.

DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thefollowing detailed description of the preferred embodiments, taken inconjunction with the accompanying drawings in which:

FIG. 1 is a fragmentary cross sectional view illustrating a portion of asingle conventional chalcogenide memory cell;

FIG. 2 is a fragmentary cross sectional view of a deposition of a layerof silicon nitride onto a substrate;

FIG. 3 is an overhead view of a cross shaped region and surroundingcavity region formed in the layer of silicon nitride;

FIG. 4 is a fragmentary cross sectional view of the cross shaped regionand surrounding cavity region formed in the layer of silicon nitride;

FIG. 5 is a fragmentary cross sectional view of a deposition of a layerof silicon dioxide onto the cross shaped region and cavity region of thesilicon nitride layer;

FIG. 6 is an overhead view of a square mask applied to the layer ofsilicon dioxide which overlaps a cross shaped upper horizontal surfaceof the silicon dioxide layer;

FIG. 7 is an overhead view of a remaining portion of the silicon dioxidelayer following an anisotropic etching process;

FIG. 8 is a fragmentary cross sectional view of the remaining portion ofthe silicon dioxide layer and the underlying silicon nitride layerfollowing the anisotropic etching process;

FIG. 9 is a fragmentary cross sectional view of the remaining portion ofthe silicon dioxide layer and underlying silicon nitride layer followinga deposition of silicon nitride;

FIG. 10 is a fragmentary cross sectional view of the remaining portionof the silicon dioxide layer and the silicon nitride layers following achemical and mechanical polish planarization;

FIG. 11 is a fragmentary cross sectional view of the openings formed inthe silicon nitride layers following a differential anisotropic etchingof the silicon dioxide and silicon nitride layers;

FIG. 12 is an overhead view of the openings formed in the siliconnitride layers following the differential anisotropic etching of thesilicon dioxide and silicon nitride layers;

FIG. 13 is a fragmentary cross sectional view of the pores formed in thesilicon nitride layers following an anisotropic etching of the siliconnitride layers;

FIG. 14 is a fragmentary cross sectional view of the final structurefollowing the final step of anisotropic etching of the remaining portionof the silicon dioxide layer;

FIG. 15 is a fragmentary cross sectional view illustrating a portion ofa chalcogenide memory cell fabricated in accordance with the method ofthe presently preferred embodiment that utilizes a single pore;

FIG. 16 is a fragmentary cross sectional view illustrating a portion ofa chalcogenide memory cell fabricated in accordance with the method ofthe presently preferred embodiment that utilizes multiple pores;

FIG. 17 is a top view of an array of cross shaped regions forfabricating an array of equally spaced groups of pores; and

FIG. 18 is a top view of an array of pores fabricated the method of thepreferred embodiment utilizing an array of cross shaped regions.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A method of fabricating pores is presented that provides pore sizessmaller than that presently provided using conventionalphotolithographic methods. The method further eliminates theunpredictable results provided by the conventional method of poreformation by dielectric breakdown of a thin silicon nitride layer. Inparticular, the preferred embodiment of the present invention provides amethod of fabricating pores that relies upon the thickness of a thinfilm of silicon dioxide, having been applied to an edge feature of anunderlying layer of silicon nitride, to define the minimum lateraldimension of the pore. In this manner, pore sizes having minimum lateraldimensions as small as around 50 to 500 Angstroms are obtained.

Turning to the drawings and referring initially to FIG. 2, a preferredembodiment of the present invention will now be described. Asillustrated in FIG. 2, a first layer 10 of silicon nitride is depositedonto a substrate 20 using conventional thin film deposition techniques.The first layer 10 of silicon nitride may have a uniform thicknessranging from approximately 1000 to 3000 Angstroms, and preferably it hasa uniform thickness of around 2400 Angstroms. The substrate willpreferably comprise a suitable material for use as a lower electrode orconductive channel for use in a chalcogenide memory cell.

The layer 10 is then etched using conventional anisotropic etchingtechniques to provide a cross shaped region 30 surrounded by a cavity 40as illustrated in FIGS. 3 and 4. The cross shaped region 30 includes anupper horizontal surface 50 and generally vertical surfaces 60 extendingdownwardly therefrom to a lower horizontal surface 70. The location ofthe cross shaped region 30 is further defined by a center point 35. Thewidth w of the horizontal surface 50 in the arms of the cross shapedregion 30 may vary from approximately 0.25 to 0.50 microns, andpreferably the width w is around 0.40 microns. The lengths L of the twoarms of the cross shaped region 30 may range from approximately 0.50 to1.00 microns from end to end, and preferably are around 0.80 microns.The etching process will remove a volume of material sufficient toreduce the thickness of the layer 10 within the cavity region 40 tobetween approximately 100 and 500 Angstroms, and preferably to around200 Angstroms.

As illustrated in FIG. 5, a layer 80 of silicon dioxide is thendeposited onto the horizontal and vertical surfaces, 50 and 60respectively, of the cross shaped region 30 and the horizontal surface70 of the cavity region 40 using conventional thin film depositiontechniques. The layer 80 of silicon dioxide includes an upper horizontalcross shaped layer 85 and vertical layers 90 extending therefrom to alower horizontal layer 95. The upper cross shaped layer 85 includescorners 86, 87, 88, and 89 defining the beginning of the arms extendingfrom the central square region of the cross shaped layer 85. The layer80 may have a uniform thickness ranging from approximately 50 to 500Angstroms, and preferably it has a uniform thickness of around 250Angstroms. The selected thickness of the layer 80 of silicon dioxidedetermines the final minimum lateral dimension of the pores fabricatedby the method of the present preferred embodiment.

A square area 100 is then masked prior to anisotropic etching of thelayer 80 of silicon dioxide using conventional etching techniques asillustrated in FIG. 6. The portion of the layer 80 of silicon dioxidemasked off within the square area 100 remains after the etching processas illustrated in FIGS. 7 and 8. The square area 100 is preferablypositioned using known techniques such that a center point 105 of thesquare area 100 is coincident with the center point 35 of the crossshaped region 30. The square area 100 is further oriented to mask foursubstantially equal square areas 110, 115, 120, and 125 within thecavity region 40. The square area 100 may range from approximately 4500to 10000 Angstroms on a side, and preferably is about 6000 Angstroms ona side. The square area 100 includes corners 101, 102, 103, and 104. Theuse of an overlapping square shaped mask overlaying the cross shapedmember 30 results in a technique of fabrication that is extremelytolerant of misalignment in the positioning of the square mask 100relative to the cross shaped member 30.

The method of the preferred embodiment provides a means ofsimultaneously fabricating four equally spaced pores for a memory cellarray that comprises four equally spaced memory cells. It furtherprovides a means of fabricating four staggered pores that serve as abasis for a memory cell array that comprises two adjacent memory cellseach including a pair of pores. It still further provides a means offabricating four staggered pores that serve as a basis for a singlememory cell that utilizes all four pores. The memory cell that utilizesall four pores is extremely tolerant of misalignment of the square mask100 and the cross shaped region 30 since the total cross sectional areaof the four pores of the memory cell will be constant regardless ofmisalignment of these features.

A second layer 130 of silicon nitride is then deposited onto the entirestructure covering the layer 80 of silicon dioxide and completelyfilling the cavity region 40 using conventional thin film depositiontechniques, as illustrated in FIG. 9. The layer 130 of silicon nitridemay be applied to provide a minimum coating thickness over the upperhorizontal cross shaped layer 85 of silicon dioxide ranging fromapproximately 500 to 3000 Angstroms, and preferably provides a minimumcoating thickness of at least about 2500 Angstroms.

The entire structure is then subjected to chemical and mechanicalpolishing (CMP) planarization using conventional techniques to provide asmooth upper planar surface and also to expose the upper portion of thevertical layers 90 of silicon dioxide as shown in FIG. 10.

The entire structure is then subjected to a dry anisotropic,differential etching process, where the etch rate for the silicondioxide is greater than that for the silicon nitride, using conventionaltechniques. The resulting structure following the differential etchingprocess includes pores 140 where the vertical layers 90 of silicondioxide have been removed as illustrated in FIG. 11. The minimum lateraldimensions x of the pores 140 are equal to the selected thickness of thelayer 80 of silicon dioxide which may range from approximately 50 to 500Angstroms, and preferably it is around 250 Angstroms. The pores 140further have L-shaped cross sections as illustrated in FIG. 12 with legsof length y. The length y will be a function of the dimensions of thesquare mask 100. Adjacent pores 140 will be spaced apart from each otherby dimension w of the arms of the cross shaped regions 30 which mayrange from approximately 0.25 to 0.5 microns, and preferably are about0.40 microns.

The larger the overlap of the square mask 100 over the cross shapedregion 30, the larger the lengths y of the legs of the L-shaped pores140. The length y of the L-shaped pores 140 will be equal to thedimension of the side of the square mask 100 minus the width w of thearms of the cross shaped region 30 divided by 2. The cross sectionalshapes of the pores 140 may be reduced to square shaped cross sectionsby proper initial selection of the cross shaped region 30 and the squaremask 100 resulting in minimum cross sectional areas for pores 140 equalto x². In particular for selection of the square mask 100 with corners101, 102, 103, and 104 coincident with corners 86, 87, 88, and 89 of thecross shaped horizontal layer 85 of silicon dioxide, the resulting crosssectional areas for the pores 140 are equal to x².

The entire structure is then subjected to an conventional anisotropicetch of the silicon nitride material which extends the pores 140 to thetop surface of the substrate 20, as illustrated in FIG. 13. Theremaining horizontal layers 95 of silicon dioxide are then removed by aconventional etching process as illustrated in FIG. 14.

Other materials may be utilized in fabricating the array of pores of thefinal structure. For example, silicon dioxide may utilized in place ofthe layers of silicon nitride and polysilicon may be utilized in placeof silicon dioxide. More generally, the teachings of the presentpreferred embodiment may be utilized to fabricate a single pore or anarray of ultra-small pores utilizing materials capable of use withconventional anisotropic etching and masking processes.

The array of pores 140 of the final structure are preferablysymmetrically positioned with respect to each other and separated fromadjacent pores by a spacing ranging from approximately 0.25 to 0.50microns as defined by the selected dimensions for the width w of thearms of the cross shaped region 30. In a preferred embodiment, the finalstructure of the present preferred embodiment includes four equallyspaced pores 140. Staggered pores 140 may be utilized for a memory cellthat employs a pair or all four of the pores since a memory cell withmultiple pores is tolerant of misalignment in previous maskingoperations.

The preferred embodiment of the present invention may be utilized tofabricate an array of phase-changeable memory cell such as, for example,a chalcogenide memory cell 200 as illustrated in FIG. 15. In fabricatingsuch chalcogenide memory cells 200 the present preferred embodiment forfabricating an array of ultra-small pores is combined with conventionalfabrication techniques utilized in the manufacture of such chalcogenidememory cells to provide one cell or an array of such chalcogenide memorycells. The memory cells fabricated utilizing the method of the preferredembodiment further may utilize a single pore, two pores, or all four ofthe pores fabricated adjacent to a cross shaped region 30.

A chalcogenide memory cell 200 is illustrated in FIG. 15 that includes alower electrode layer 205, a dielectric layer 210 including a singlepore 215, a layer of a chalcogenide memory material 220 including achalcogenide active region 225, and an upper electrode layer 230. Thepore 215 is formed by the method of the present preferred embodimentwhich provide a group of four equally spaced pores. The remainingstructure of the memory cell 200 is formed using conventional thin filmdeposition and etching techniques. Thus a group of four closely spacedchalcogenide memory cells 200 may be provided by the group of four poresfabricated adjacent to a single cross shaped region 30.

A chalcogenide memory cell is illustrated in FIG. 16 that utilizes twoor all four of the ultra-small pores formed by the method of presentpreferred embodiment. The chalcogenide memory cell 300 includes a lowerelectrode layer 305, a dielectric layer 310 including pores 315, a layerof a chalcogenide memory material 320 including chalcogenide activeregions 325, and an upper electrode layer 330. The pores 315 are formedby the method of the present preferred embodiment. The remainingstructure of the memory cell 300 is formed using conventional thin filmdeposition and etching techniques. The chalcogenide memory cell 300 thusformed is centrally positioned over the four pores formed adjacent to asingle cross shaped member 30 by the method of the present preferredembodiment.

The method of the presently preferred embodiment thus provides a meansof fabricating memory cells that utilize one or more pores. Inparticular, the use of all four pores in a memory cell results in astructure that is extremely tolerant of misalignment in the previousmasking processes since the total cross sectional area of the pores usedwill be constant. Likewise a memory cell that employs a pair of adjacentpores will also be tolerant of misalignment.

More generally, the fabrication techniques of the present preferredembodiment may be utilized to fabricate an array of such pores byetching an array of interconnected cross shaped regions 30 in the firstlayer 10 as illustrated in FIG. 17. The interconnected cross shapedregions 30 are spaced apart by cavity regions 400. Utilizing the methodof the presently preferred embodiment, such a structure providesadjacent groupings of such pores 140 equally spaced from other groupingsto thereby form a matrix of such pores 140 as illustrated in FIG. 18.

By providing a chalcogenide memory cell centered at a single pore orcentered over all four pores fabricated adjacent a cross shaped memberby the method of the presently preferred embodiment an array of memorycells is produced. This is facilitated by providing, in a well knownmanner, a substrate that includes a corresponding array of conductiveregions which provide lower electrodes for each of the memory cells.These memory cells are preferably made individually addressable byfurther providing an x-y matrix of conductive channels above and belowthe memory cells, in a well known manner, as disclosed in U.S. Pat. No.5,296,716 to Ovshinsky et al. Preferably these individually addressablememory cells are also electrically isolated from other memory cells inthe array, in a well known manner, by the addition of diodes or othersimilar access devices which are connected in series between each memorycell and one of the x-y conductive channels as also disclosed in theaforementioned Ovshinsky patent.

Typical chalcogenide compositions for these memory cells include averageconcentrations of Te in the amorphous state well below 70%, typicallybelow about 60% and ranging in general from as low as about 23% up toabout 56% Te and most preferably to about 48% to 56% Te. Concentrationsof Ge are typically above about 15% and range from a low of about 17% toabout 44% average in the high resistance state, remaining generallybelow 50% Ge, with the remainder of the principal constituent elementsin this class being Sb. The percentages given are atomic percentageswhich total 100% of the atoms of the constituent elements. In aparticularly preferred embodiment, the chalcogenide compositions forthese memory cells comprise a Te concentration of about 55%, a Geconcentration of about 22%, and a Sb concentration of about 22%. Thisclass of materials are typically characterized asTe_(a)Ge_(b)Sb_(100−(a+b)), where a is equal to or less than about 70%and preferably between about 60% to about 40%, b is above about 15% andless than 50%, preferably between about 17% to about 44% and theremainder is Sb.

A method for fabricating ultra-small pores in a layer of a firstmaterial has been presented for use in providing pores whose minimumlateral dimensions are defined by the thickness of a layer of a secondmaterial applied to an edge feature of the first material. In anexemplary embodiment, the method provides pores having a minimum lateraldimension of about 500 Angstroms with a minimum cross sectional area ofabout 0.03 microns². The method further provides a means of fabricatingan array of pores simultaneously to thereby permit a grid ofchalcogenide memory cells to be grouped together in close proximity.

The present method may be used to provide pores in a layer of materialusing raised surfaces with vertical depending surfaces having geometriesother than the cross shaped surface disclosed in the description of thepreferred embodiment. More generally the teachings of the present methodenable the fabrication of ultra small pores based upon any edge featureof a material layer and may be further used to fabricate one or aplurality of such pores simultaneously.

While the invention is susceptible to various modifications andalternative forms, specific embodiments have been shown by way ofexample in the drawings and will be described in detail herein. However,it should be understood that the invention is not intended to be limitedto the particular forms disclosed. Rather, the invention is to cover allmodifications, equivalents, and alternatives falling within the spiritand scope of the invention as defined by the appended claims.

What is claimed is:
 1. A chalcogenide memory cell, comprising: an upperelectrode; a lower electrode; a dielectric layer positioned between saidupper and lower electrodes and including an opening defining a pore; achalcogenide element within said pore, said chalcogenide elementelectrically coupled to said upper and lower electrodes; wherein saidpore has a minimum lateral dimension ranging from about 50 to 500Angstroms.
 2. The chalcogenide memory cell of claim 1, wherein said porehas an L shaped cross section.
 3. A memory cell comprising: an upperelectrode; a lower electrode; dielectric material positioned between theupper electrode and the lower electrode, the dielectric material havinga pore therein, the pore having an L-shaped cross section; and memorymaterial disposed within the pore, the memory material beingelectrically coupled to the upper electrode and to the lower electrode.4. The memory cell, as set forth in claim 3, wherein the pore comprisesa minimum lateral dimension in a range from about 50 to about 500Angstroms.
 5. The memory cell, as set forth in claim 3, wherein thedielectric material comprises a lateral dimension on each side of thepore in a range between about 0.25 and about 0.50 microns.
 6. The memorycell, as set forth in claim 3, wherein the memory element comprises achalcogenide material.
 7. A memory cell comprising: an upper electrode;a lower electrode; dielectric material disposed between the upperelectrode and the lower electrode, the dielectric materail having atleast two pores formed therein extending from the upper electrode to thelower electrode; and a memory element disposed within each of the pores.8. The memory cell, as set forth in claim 7, wherein the memory elementcomprises a chalcogenide material.
 9. The memory cell, as set forth inclaim 7, wherein a minimum lateral dimension of each pore ranges fromabout 50 to 500 Angstroms.
 10. The memory cell, as set forth in claim 7,wherein each of the pores comprises an L-shaped cross section.
 11. Thememory cell, as set forth in claim 7, wherein the dielectric materialcomprises four pores formed therein extending from the upper electrodeto the lower electrode.
 12. The memory cell, as set forth in claim 11,wherein the four pores are symmetrically arranged.
 13. The memory cell,as set forth in claim 11, wherein the four pores are equally spaced fromone another.
 14. The memory cell, as set forth in claim 7, wherein eachof the pores comprises a square-shaped cross section.